1. Field
Exemplary embodiments of the present invention relate generally to a semiconductor design technology and, more particularly, to a duty cycle correction (DCC) circuit and a duty cycle correction method.
2. Description of the Related Art
In integrated circuit chips, such as for example, a CPU, a memory device, and the like, which operate based on a clock, it is very important to accurately control a clock duty cycle. For example, in a memory where data is inputted/outputted at a rising edge and a falling edge of a clock. When the clock duty cycle is not precisely 50%, the timing between the rising edge and the falling edge may be distorted, and thus data may be inputted/outputted at incorrect times. For reference, a clock duty cycle of 50% means that a high level period is substantially equal to a low level period.
Therefore, in various integrated circuit chips operating on a clock, a duty cycle correction circuit is typically employed for correcting the clock duty cycle. FIG. 1A is a block diagram illustrating a conventional duty cycle correction circuit. FIG. 1B is a waveform diagram illustrating an operation of the conventional duty cycle correction circuit of FIG. 1A.
Referring to FIG. 1A, the duty cycle correction circuit includes a receiver 110, a driver 120, a duty cycle detector 130, and a duty cycle corrector 140.
The receiver 110 receives clocks CLK and CLKB inputted to the duty cycle correction circuit. The driver 120 drives output clocks CLK_OUT and CLKB_OUT in response to input clocks CLK_IN and CLK_INB outputted from the receiver 110. The duty cycle detector 130 detects duty cycles of the output clocks CLK_OUT and CLKB_OUT. Here, detecting the duty cycles means identifying whether high level periods (“Ta” in FIG. 1B) or low level periods (“Tb” in FIG. 1B) of the output clocks CLK_OUT and CLKB_OUT are longer than the other one. The duty cycle corrector 140 corrects duty cycles of the input clocks CLK_IN and CLK_INB depending on duty correction values DCC_OUT and DCC_OUTB outputted from the duty cycle detector 130.
Referring to FIG. 1B, when the duty cycle detector 130 determines that the high level periods Ta of the output clocks CLK_OUT and CLKB_OUT are relatively longer than the low level periods Tb, the duty cycle corrector 140 increases the low level periods of the input clocks CLK_IN and CLK_INB. In an opposite case, the duty cycle corrector 140 increases the high level periods of the input clocks CLK_IN and CLK_INB. Since the driver 120 employs a clock received by the receiver 110 and a duty correction value from the duty cycle corrector 140 as the input thereof, the duty corrected output clocks CLK_OUT and CLKB_OUT are outputted from the driver 120.
As described above, such a feedback-type duty cycle correction circuit increases or decreases the high level periods of the input clocks CLK_IN and CLK_INB at small increments or decrements using a feedback duty cycle detection result, and is locked when the degree of distortion of the duty cycle is reduced below a predetermined margin. That is to say, the duty cycle correction circuit operates similarly to a delay-locked loop (DLL), and requires a separate locking time until the duty cycle is corrected, like the delay-locked loop.
When a locking time is required before the duty cycle is corrected, a device repeatedly transitioned from or to a standby mode such as an idle mode to or from an operation mode such as an active mode, must wait for the locking time to correct the duty cycle on a wake-up time at which a transition is made from the idle mode to the active mode.